library verilog;
use verilog.vl_types.all;
entity exp2 is
    port(
        mode_choose     : in     vl_logic_vector(7 downto 0);
        input_data      : in     vl_logic_vector(7 downto 0);
        led_out         : out    vl_logic_vector(11 downto 0)
    );
end exp2;
